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15. H. Ahmadi and W. E. Denzel, A survey of modern high-performance switching techniques, IEEE J. Sel. , 7: 1091–1103, 1989. 16. K. Y. Lee and D. Lee, On the augmented data manipulator network in SIMD environments, IEEE Trans. , 37: 574– 584, 1988. 17. H. J. , Using the multistage cube network topology in parallel supercomputers, Proc. IEEE, 77: 1932–1953, 1989. 18. C. E. Leiserson, Fat-trees: Universal networks for hardware-efficient supercomputing, IEEE Trans. , C-34: 892–901, 1985. 19. L. M.

If the message is closer to its destination than d, then the protocol switches to an exhaustive misrouting search. Because the second phase can route the message further away from its destination again, the search may switch between the two phases multiple times. SWITCH BOX ARCHITECTURES The architecture of the switch boxes depends on the underlying switching mechanism (see the section ‘‘Switching Techniques’’ above) and has a large effect on network performance. This section discusses architectural issues with respect to switch boxes and their effect on network performance.

Assume that a message is currently routed through switch 2 from port D to port E. This message blocks another message that enters switch 1 at port A, which is destined to port E as well. The head flit will wait in the flit buffer at input port C. However, this message blocks a third message entering switch 1 at port B that is destined to port F. In this example, two messages are blocked because port E is currently unavailable. To alleviate this problem, virtual channels were introduced (20). As depicted in Fig.

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