By Liza Fireman, Erez Petrank, Ayal Zaks (auth.), Shriram Krishnamurthi, Martin Odersky (eds.)
This ebook constitutes the refereed lawsuits of the sixteenth overseas convention on Compiler building, CC 2007, held in Braga, Portugal, in March 2007 as a part of ETAPS 2007, the eu Joint meetings on thought and perform of Software.
The 15 revised complete papers awarded have been rigorously reviewed and chosen from 60 submissions. The papers are geared up in topical sections on structure, rubbish assortment and software research, sign in allocation, and software analysis.
Read or Download Compiler Construction: 16th International Conference, CC 2007, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2007, Braga, Portugal, March 26-30, 2007. Proceedings PDF
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Additional info for Compiler Construction: 16th International Conference, CC 2007, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2007, Braga, Portugal, March 26-30, 2007. Proceedings
36 K. Shyam and R. Govindarajan MWPC, arrays a and b will be allocated to memory bank M 1 and c and d to memory bank M 2. For this allocation, the memory banks that are active in each loop and the bank-cycles for which the memory is active are shown in Table 1. We see that memory is active for a total of 26N bank-cycles. Although the MWPC method correctly identiﬁes that edge (b, c) has a large weight, the requirement to allocate arrays to memory banks in the order in which they appear in the MWPC causes the bad decision in this example.
We have implemented Algorithm 1 for our array allocation heuristic. The output of the heuristic is the partition of arrays into diﬀerent memory banks. For the Integer Linear Programming problem formulation we have used the commercial solver CPLEX R . From the partition obtained from the heuristic or CPLEX solver, we derive the declaration order of the arrays (with appropriate padding) to enforce the partition to diﬀerent memory banks. We also make necessary modiﬁcations to accommodate arrays whose sizes are greater than the memory banks.
This is not a coincidence, since our algorithm is designed to apply cloning1 and cloning2 only when the additional operations for these techniques can be placed in non-critical recurrence circuits. Figure 8(b) reports code size increase due to the unified algorithm. Since cloning1 and cloning2 reduces ExRecMII, existing modulo scheduler discovers instruction level parallelism across more loop iteration boundary and as a result, achieves a better modulo schedule. Since the size of the prologue and the epilogue grow proportionally as more loop iterations of a candidate loop get overlapped for a final schedule, code size increase is unavoidable.