By Robert Beers, Rajnish Ghughal, Mark Aagaard (auth.), Warren A. Hunt Jr., Steven D. Johnson (eds.)
The biannual Formal equipment in machine Aided layout convention (FMCAD 2000)is the 3rd in a chain of meetings lower than that name dedicated to using discrete mathematical tools for the research of machine and so- ware. The paintings suggested during this booklet describes using modeling languages and their linked computerized research instruments to specify and ensure computing structures. useful veric ation has develop into one of many vital expenses in a contemporary desktop layout e ort. In addition,verica tion of circuit versions, timing,power, etc., calls for much more eo rt. FMCAD presents a venue for tutorial and - dustrial researchers and practitioners to proportion their rules and stories of utilizing discrete mathematical modeling and veric ation. it truly is famous with curiosity by way of the convention chairmen how this quarter has grown from quite a few humans 15 years in the past to a colourful quarter of analysis, improvement, and deployment. it's transparent that those tools are supporting lessen the price of designing computing platforms. for example of this strength rate relief, we've got invited David Russino of complicated Micro units, Inc. to explain his veric ation of ?oating-point - gorithms getting used in AMD microprocessors. this system comprises 30 general shows chosen from sixty three submitted papers.
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Extra info for Formal Methods in Computer-Aided Design: Third International Conference, FMCAD 2000 Austin, TX, USA, November 1–3, 2000 Proceedings
Example text
The formal design of 1m-gate ASICs. In P. Windley and G. Gopalakrishnan, editors, Formal Methods in CAD, pages 49–63. Springer Verlag; New York, Nov. 1998. 10. M. Gordon. Programming combinations of deduction and BDD-based symbolic calculation. Technical Report 480, Cambridge Comp. Lab, 1999. 11. IEEE. IEEE Standard for binary floating-point arithmetic. ANSI/IEEE Std 754-1985, 1985. 12. -Y. Jang, S. Qadeer, M. Kaufmann, and C. Pixley. Formal verification of FIRE: A case study. In DAC, pages 173–177, June 1997.
In most situations, many sound decomposition techniques are applicable, but most will not be helpful in mitigating the capacity limitations of model checking. Picking an effective decomposition technique requires knowledge of both the circuit being verified and the model checker being used. g. the ordering of temporal or Boolean operators) dramatically affect the memory usage or runtime of a verification. Over time, our group developed heuristics for writing specifications so as to extract the maximum capacity from the model checker.
Manb[67:0] : mana[67:0]; //*********************************************************************************** // Second Cycle //*********************************************************************************** //PREDICT EXPONENT OF RESULT// lshift[17:0] = far ? (esub ? 18’h3ffff : 18’b0) : ~{11’b0,lsa[6:0]}; exp[17:0] = expl[17:0] + lshift[17:0]; //ALIGN OPERANDS// ina_close[68:0] = ~shift_close & (mana < manb) ? inb_swap_close[68:0] << lsa[6:0] : ina_swap_close[68:0] << lsa[6:0]; ina_add[70:0] = far ?