By Chester Rebeiro, Debdeep Mukhopadhyay, Sarani Bhattacharya
This booklet offers with timing assaults on software program implementations of encryption algorithms. It describes and analyzes a variety of unintentional covert timing channels which are shaped while ciphers are completed in microprocessors. sleek superscalar microprocessors are thought of, that are enabled with positive factors reminiscent of multi-threaded, pipelined, parallel, speculative, and out-of-order execution. a number of timing assault algorithms are defined and analyzed for block ciphers in addition to public-key ciphers. The interaction among the cipher implementation, method structure, and the attack's luck is analyzed. extra and software program countermeasures are mentioned with the purpose of illustrating tips on how to construct structures that could defend opposed to those assaults.
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Extra info for Timing Channels in Cryptography
Zheng Y, Matsumoto T, Imai H (1989) On the construction of block ciphers provably secure and not relying on any unproved hypotheses. In: Brassard G (ed) CRYPTO. Lecture notes in computer science, vol 435. Springer, Berlin, pp 461–480 3. Federal Information Processing Standards Publication 197 (2001) Announcing the Advanced Encryption Standard (AES) 4. Stinson D (2002) Cryptography: theory and practice, 2nd edn. Chapman and Hall, London, pp 117–154 5. Daemen J, Rijmen V (2002) The design of Rijndael: AES—the Advanced Encryption Standard.
Massey J (1994) Guessing and entropy. In: Information theory, 1994. Proceedings, 1994 IEEE international symposium, 1994, p 204 Chapter 3 Superscalar Processors, Cache Memories, and Branch Predictors Memory accesses and branches are arguably the biggest performance bottlenecks in a program. To mitigate their effect on the performance, modern superscalar microprocessors incorporate cache memories and branch predictors in their architecture. While cache memories bridge the performance gap between the processor and the main memory, branch predictors make predictions about branch destinations to reduce the overhead of branches in the program.
4 Direct mapped cache memory with 2b = 4 Lines in Cache Memory Blocks in Main Memory translation mechanism is required to determine which cache line a block should get stored into. In the most simple approach, every 2b -th memory block gets mapped into the same cache line. This mapping is called direct-mapping and is depicted in Fig. 4. The address translation mechanism computes two components: the word address Aword and the line address Aline . If A is the address of the data that is to be accessed then Aword = A mod 2δ Aline = A/2δ mod 2b .